When actualizing a central processing unit, which will be referred to as a CPU hereinafter, on a large-scale integrated circuit, it is preferable that the system of the central processing unit comprise many elements having a regular structure, such as those of general-purpose registers, read only memory or the like, since elements having irregular logical structure, such as arithmetic-logic units, instruction decoders or the like are relatively large in scale. Elements having regular structure on the other hand have small wiring areas so that a high-density circuit arrangement can be adopted. Generally speaking, general-purpose registers in a CPU are capable of performing high-speed access compared to a main storage device so that it is possible to execute high-speed processing such as the operation of complex data of a large number, by building in a number of general-purpose registers. However, when an interrupt request is applied to the CPU, it is often necessary to save the data stored in the general-purpose registers in the main memory prior to the execution of the interrupt service routine. Therefore, if the number of the general-purpose registers is great, the number of times that data are transferred from the registers to the CPU is also great, so that it takes a relatively long period of time from the time of application of the interrupt request until the initialization of the interrupt service routine. In the same manner, it takes a relatively long period of time when returning to the original program from the interrupt service routine. Accordingly, in case there are a number of interrupt priority levels, and the program is such that a number of input/output devices are controlled, the processing of the interrupt service routines will be delayed if interrupt requests are frequently applied while the number of the registers used therefor is great.
For a better understanding of the present invention a conventional and most typical method of interrupt processing will be described with reference to FIG. 1. In FIG. 1, a reference numeral 11 represents a main memory or storage device, 12 a register (PSWR) which stores or holds a program status word (PSW). A PSW includes various information indicative of the state of a running program, such as the count of the program counter (not shown), the content of the arithmetic status register (not shown) and the like. A reference numeral 13 represents a general-purpose register (GR), and these registers 12 and 13 are included in a central processing unit CPU. An initial value of the program status word register PSWR for initializing the execution of the interrupt service routine, i.e. a new program status word (NPSWR) is prestored in a particular region 14 of the main memory 11. A region designated at a reference 15 in the main memory 11 is used for saving the data of the PSWR 12 and the general-purpose register 13 on execution of an interrupt service routine. This region 15 may be referred to as a saving region.
When an interrupt request is acknowledged, the contents of the PSWR 12 and the GR 13 are transferred to respective specific regions corresponding to the interrupt priority levels in the saving region 15, and then an NPSWR corresponding to the interrupt priority level is selected from the region 14 to be transferred to the PSWR and then the execution of the program of the interrupt service routine is started. As the interrupt service routine has been completed, and in case of turning to the execution of the original program, the information or data saved in the saving region 15 are transferred to the PSWR 12 and GR 13 thereby resuming the execution of the original program. As described in the above, in the conventional example of FIG. 1, it is necessary to transfer the contents of the PSWR 12 and GR 13 between the CPU and the main memory 11 at the time of initialization and termination of the interrupt service so that it takes a relatively long period of time to respond to or handle an interrupt service.
FIG. 2 also illustrates a conventional example, and in this example, a plurality of internal registers of the CPU are divided into several groups or sets in order to improve the response time for interrupt services. Reference numerals 21, 22, 23 and 24 respectively represent first, second, third and fourth register-sets. All of the register-sets have the same construction, and each of the register-sets consists of a PSWR and a general-purpose register GR to assume either an active state or a hold state. References E1, E2, E3 and E4 are signals which determine whether a corresponding register-set is put in the active state or in the hold state. References INT1, INT2 and INT3 represent interrupt request signals, and it is assumed that a smaller number indicates a higher priority level. Flip-flops IF1, IF2 and IF3 are respectively responsive to the above-mentioned interrupt requests, and each of the flip-flops IF1 to IF3 is set when the logic level of its interrupt request signal turns to "1" from "0". A reference numeral 25 represents a priority control circuit which changes the logic level of one signal among the above-mentioned signals E1 to E4 to "1" by checking the highest priority level set in the flip-flops IF1 to IF3. In case all of the flip-flops IF1 to to IF3 have been reset, only E4 becomes logic "1". Accordingly, when there is no interrupt request, only the fourth register 24 is in the active state, while other three registers 21 to 23 are in the hold state. Under this condition, it is assumed that an interrupt request of the second level has occurred. Accordingly, the logic level of the signal INT2 becomes "1" to set the second flip-flop IF2. As a result, the output E2 of the priority control circuit 25 turns to logic "1", while the output E4 turns to logic "0" . Consequently, the fourth register-set 24 returns to its hold state, while the second register-set 22 turns to its hold state. There is no need to save the contents of the register-sets in the main memory as in the system of FIG. 1 so that the second register-set will be used for the execution of the interrupt service routine program. Furthermore, if initial values NPSW corresponding to respective levels have been prestored in the PSWR of respective register-sets, there is no need to fetch a PSW from the main memory at the time of occurrence of an interrupt request. In case that the interrupt service routine of the second level has been completed, the execution of the original program, which has been suspended, will start by resetting the flip-flop IF2 to cause the logic level of the signal E2 to become "0" again when a return-from-interrupt service routine instruction is executed. Also when an interrupt request of the first level occurs during the execution of the interrupt service routine of the first level, the CPU can respond quickly in the same manner. It will be recognized that in such a system having four registers, prior execution of interrupt service routines can be performed at high-speed with as many as four priority levels.
However, such a system has the following drawbacks.
(1) Since it is necessary to prestore a PSW in each PSWR of respective register-sets by a program, it is difficult to maintain an interchangeability between systems having different numbers of register-sets.
(2) The number of priority interrupt levels cannot be increased more than the number of the register-sets.